Electrical Metrics for Lithographic Line-End Tapering

A major source of patterning problems in low-k1 lithography is line-end pullback. Though geometric metrics such as CD at gate edge have served as good indicators, the ever-rising contribution of line-end extension to layout area necessitates reducing pessimism in qualifying line-end patterning. Electrically-aware metrics for line-ends can be helpful in this regard. In this work, we calculate the Ion and Io f f impact of line-end taper shapes as well as line-end length. The proposed models are verified using TCAD simulation in a typical 65nm process. We observe that the device threshold voltage is a weak function of line-end pullback, and that the electrical impact of the taper can vary with overlay errors. We apply a non-uniform channel length model in addition to the proposed taper-dependent threshold voltage model to calculate ∆Ion and ∆Io f f . Finally, the electrical metric for line-end printing is defined as expected change in Ion or Io f f under a given overlay error distribution. We also propose a super-ellipse form to parameterize taper shapes, and then explore a large variety of taper shapes to characterize electrical impact.